Synchronous Dynamic Random Access Memory (SDRAM) devices typically include an internal clock generation circuit that generates an internal clock signal that is locked to an external reference clock signal. The generated internal clock signal may be used in the generation of internal signals that are used to operate the SDRAM device and to control data input and output operations.
FIG. 1 is a block diagram of a conventional internal clock generation circuit 100 that may be used, for example, in an SDRAM device. The conventional internal clock generation circuit 100 includes a fine locking block 160, a Voltage Controlled Delay (VCD) block 130 and a Delay Mirror Circuit (DMC) 150. The fine locking block 160 includes a Phase Detector (PD) 161, a Charge Pump (CP) 163, and a Loop Filter (LF) 165, which are used to generate a voltage control signal VCONT. The voltage control signal VCONT controls the delay time of the VCD 130 so that the phase of a detection clock signal TCLK matches the phase of a buffered clock signal BCLK. As a result, the phase of an internal clock signal ICLK ultimately matches the phase of an external clock signal ECLK. However, a locking time of several hundred to several thousand cycles may be required to lock the phase of the internal clock signal ICLK to the phase of the external clock signal ECLK using the conventional internal clock generation circuit 100 of FIG. 1.
Analog Synchronous Mirror Delay (ASMD) circuits may also be used to generate an internal clock signal that is synchronized with an external reference clock signal. With such ASMD circuits, an output clock signal may be locked to a received clock signal with a locking time of as little as two clock cycles. However, conventional ASMD circuits may have a narrow operating range. Thus, they may not be able to cope with frequency variation in a received clock signal.